struppi/rgbyteclock-hw
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add >name and >value to poti

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add license
This commit is contained in:
daniel steuer 2014-03-06 16:42:20 +01:00
parent 03f9df44a7
commit bc48e4a511
2 changed files with 13 additions and 7 deletions
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16
rgbyteclock.brd
View File

@ -112,13 +112,17 @@
<hole x="77.5" y="47.5" drill="2.5"/>
<hole x="2.5" y="47.5" drill="2.5"/>
<text x="7" y="4" size="2" layer="1" font="vector" ratio="16">RGByteclock</text>
<text x="7" y="1.5" size="2" layer="1" font="vector" ratio="16">v1.1</text>
<text x="7" y="1.5" size="2" layer="1" font="vector" ratio="16">v1.2</text>
<text x="7" y="4" size="2" layer="29" font="vector" ratio="16">RGByteclock</text>
<text x="7" y="1.5" size="2" layer="29" font="vector" ratio="16">v1.1</text>
<text x="7" y="1.5" size="2" layer="29" font="vector" ratio="16">v1.2</text>
<hole x="2.5" y="2.5" drill="2.5"/>
<hole x="77.5" y="2.5" drill="2.5"/>
<text x="14.5" y="1.75" size="1.2" layer="29" font="vector" ratio="16">www.bytewerk.org</text>
<text x="14.5" y="1.75" size="1.2" layer="1" font="vector" ratio="16">www.bytewerk.org</text>
<text x="60.75" y="5" size="1.2" layer="1" font="vector" ratio="16">Creative Commons</text>
<text x="60.75" y="3.5" size="1.2" layer="29" font="vector" ratio="16">CC-BY v4.0</text>
<text x="60.75" y="5" size="1.2" layer="29" font="vector" ratio="16">Creative Commons</text>
<text x="60.75" y="3.5" size="1.2" layer="1" font="vector" ratio="16">CC-BY v4.0</text>
</plain>
<libraries>
<library name="mcp2210">
@ -1177,7 +1181,7 @@ design rules under a new name.</description>
<element name="PAD5" library="wirepad" package="SMD1,27-2,54" value="" x="7.5" y="6" rot="MR90"/>
<element name="PAD6" library="wirepad" package="SMD1,27-2,54" value="" x="24.75" y="37" rot="MR90"/>
<element name="C6" library="bytewerk-passive" package="C0603" value="100n" x="41" y="27.25" rot="MR270"/>
<element name="R12" library="bytewerk-passive" package="PVZ2" value="" x="65.75" y="21.5">
<element name="R12" library="bytewerk-passive" package="PVZ2" value="10k" x="65.75" y="21.5">
<attribute name="MPN" value="PVZ2*" x="65.75" y="21.5" size="2" layer="27" display="off"/>
<attribute name="OC_FARNELL" value="1771724" x="65.75" y="21.5" size="2" layer="27" display="off"/>
</element>
@ -1252,9 +1256,9 @@ design rules under a new name.</description>
<wire x1="10.75" y1="16.25" x2="9" y2="16.25" width="0.2" layer="1"/>
<wire x1="9" y1="16.25" x2="8.65" y2="15.9" width="0.2" layer="1"/>
<wire x1="8.65" y1="15.9" x2="8.65" y2="14.5" width="0.2" layer="1"/>
<wire x1="67.75" y1="4.75" x2="69" y2="4.75" width="0.2" layer="16"/>
<via x="69" y="4.75" extent="1-16" drill="0.3"/>
<wire x1="69" y1="4.75" x2="69" y2="5.25" width="0.2" layer="1"/>
<wire x1="67.75" y1="4.75" x2="67.75" y2="2.75" width="0.2" layer="16"/>
<via x="67.75" y="2.75" extent="1-16" drill="0.3"/>
<wire x1="67.75" y1="2.75" x2="68.25" y2="2.75" width="0.2" layer="1"/>
<wire x1="40" y1="21.65" x2="40" y2="20.5" width="0.2" layer="16"/>
<via x="40" y="20.5" extent="1-16" drill="0.3"/>
<wire x1="40" y1="20.5" x2="40" y2="19.2" width="0.2" layer="1"/>

4
rgbyteclock.sch
View File

@ -3597,6 +3597,8 @@ SOT340-1 / JEDEC MO-150AG</description>
<wire x1="0" y1="-1.905" x2="0" y2="-1.27" width="0.1524" layer="94"/>
<wire x1="0" y1="-1.27" x2="1.905" y2="2.54" width="0.1524" layer="94"/>
<wire x1="1.905" y1="2.54" x2="1.27" y2="1.905" width="0.1524" layer="94"/>
<text x="0" y="1.524" size="1.27" layer="95" align="bottom-right">&gt;NAME</text>
<text x="0" y="-1.524" size="1.27" layer="96" align="top-left">&gt;VALUE</text>
</symbol>
</symbols>
<devicesets>
@ -5623,7 +5625,7 @@ Source: http://www.atmel.com/dyn/resources/prod_documents/doc2593.pdf</descripti
<part name="PAD6" library="wirepad" deviceset="SMD2" device=""/>
<part name="C6" library="bytewerk-passive" deviceset="C" device="0603" value="100n"/>
<part name="GND1" library="supply1" deviceset="GND" device=""/>
<part name="R12" library="bytewerk-passive" deviceset="R_TRIM" device=""/>
<part name="R12" library="bytewerk-passive" deviceset="R_TRIM" device="" value="10k"/>
</parts>
<sheets>
<sheet>